1. Field of the Invention
This invention relates to a Joint Test Action Group interface, and particularly to the implementation of the Joint Test Action Group interface in conjunction with source synchronous interfaces.
2. Description of Background
Joint Test Action Group (JTAG) is the name given to the IEEE 1149.1 standard for the interface enabled testing of the connectivity between sub-blocks of integrated circuits (ICs) contained within printed circuit boards by way of boundary scanning. A conventional architecture for implementing a JTAG structural configuration 100 is shown in FIG. 1. As shown in FIG. 1, within a source synchronous interface (e.g., such as DDR memory) the multiplexer 120 adds delay to the path between the I/O driver 125 and the functional register 110 and the JTAG register 105.
Generally, for interfaces such as memory, there are often many of the structures of FIG. 1 built in parallel in order to construct a bussed signal. Within such interfaces, skew between the outputs needs to be minimized in order to maximize system level timing margins. Further, manufacturing variation between the many multiplexers will introduce undesired skew between the signals in the bus which will limit the maximum clock rate that can be used on this interface.